- segment descriptor cache
- кэш сегментных дескрипторов
The New English-Russian Dictionary of Radio-electronics. F.V Lisovsky . 2005.
segment descriptor cache
Смотреть что такое "segment descriptor cache" в других словарях:
ESDC — Extra Segment Descriptor Cache … Acronyms
SSDC — • Stack Segment Descriptor Cache • System Safety Development Center ( > IEEE Standard Dictionary ) … Acronyms
ESDC — Extra Segment Descriptor Cache … Acronyms von A bis Z
SSDC — [1] Stack Segment Descriptor Cache [2] System Safety Development Center ( > IEEE Standard Dictionary ) … Acronyms von A bis Z
CSDC — abbr. Circuit Switched Digital Capability abbr. Code Segment Descriptor Cache (register) (CS, Intel, CPU) acronym Circuit Switched Digital Capability … United dictionary of abbreviations and acronyms
DSDC — abbr. Data Segment Descriptor Cache (register) (DS, Intel, CPU) … United dictionary of abbreviations and acronyms
ESDC — abbr. Extra Segment Descriptor Cache (register) (ES, Intel, CPU) … United dictionary of abbreviations and acronyms
SSDC — abbr. Stack Segment Descriptor Cache (register) (SS, Intel, CPU) … United dictionary of abbreviations and acronyms
TSSDC — abbr. Task State Segment Descriptor Cache (CPU) … United dictionary of abbreviations and acronyms
x86 — This article is about Intel microprocessor architecture in general. For the 32 bit generation of this architecture which is also called x86 , see IA 32. x86 Designer Intel, AMD Bits 16 bit, 32 bit, and/or 64 bit Introduced 1978 Design … Wikipedia
Unreal mode — Unreal mode, also big real mode, huge real mode, or flat real mode, is a variant of real mode (PE=0), in which one or more data segment registers have been loaded with 32 bit addresses and limits. Contrary to its name, it is not a separate… … Wikipedia
